/*
 * system.h - SOPC Builder system and BSP software package information
 *
 * Machine generated for CPU 'nios2_qsys_0' in SOPC Builder design 'qsys_eth'
 * SOPC Builder design path: D:/Rabota/Multispectr/ProjectDevelopment/PtSi/Firmware/DE2-115/ptsi-ctrl/trunk/qsys_eth.sopcinfo
 *
 * Generated: Wed Dec 10 11:05:56 MSK 2014
 */

/*
 * DO NOT MODIFY THIS FILE
 *
 * Changing this file will have subtle consequences
 * which will almost certainly lead to a nonfunctioning
 * system. If you do modify this file, be aware that your
 * changes will be overwritten and lost when this file
 * is generated again.
 *
 * DO NOT MODIFY THIS FILE
 */

/*
 * License Agreement
 *
 * Copyright (c) 2008
 * Altera Corporation, San Jose, California, USA.
 * All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 *
 * This agreement shall be governed in all respects by the laws of the State
 * of California and by the laws of the United States of America.
 */

#ifndef __SYSTEM_H_
#define __SYSTEM_H_

/* Include definitions from linker script generator */
#include "linker.h"


/*
 * CPU configuration
 *
 */

#define ALT_CPU_ARCHITECTURE "altera_nios2_qsys"
#define ALT_CPU_BIG_ENDIAN 0
#define ALT_CPU_BREAK_ADDR 0x8021820
#define ALT_CPU_CPU_FREQ 50000000u
#define ALT_CPU_CPU_ID_SIZE 1
#define ALT_CPU_CPU_ID_VALUE 0x00000000
#define ALT_CPU_CPU_IMPLEMENTATION "fast"
#define ALT_CPU_DATA_ADDR_WIDTH 0x1c
#define ALT_CPU_DCACHE_LINE_SIZE 0
#define ALT_CPU_DCACHE_LINE_SIZE_LOG2 0
#define ALT_CPU_DCACHE_SIZE 0
#define ALT_CPU_EXCEPTION_ADDR 0x8010020
#define ALT_CPU_FLUSHDA_SUPPORTED
#define ALT_CPU_FREQ 50000000
#define ALT_CPU_HARDWARE_DIVIDE_PRESENT 0
#define ALT_CPU_HARDWARE_MULTIPLY_PRESENT 1
#define ALT_CPU_HARDWARE_MULX_PRESENT 0
#define ALT_CPU_HAS_DEBUG_CORE 1
#define ALT_CPU_HAS_DEBUG_STUB
#define ALT_CPU_HAS_JMPI_INSTRUCTION
#define ALT_CPU_ICACHE_LINE_SIZE 32
#define ALT_CPU_ICACHE_LINE_SIZE_LOG2 5
#define ALT_CPU_ICACHE_SIZE 4096
#define ALT_CPU_INST_ADDR_WIDTH 0x1c
#define ALT_CPU_NAME "nios2_qsys_0"
#define ALT_CPU_NUM_OF_SHADOW_REG_SETS 0
#define ALT_CPU_RESET_ADDR 0x8010000


/*
 * CPU configuration (with legacy prefix - don't use these anymore)
 *
 */

#define NIOS2_BIG_ENDIAN 0
#define NIOS2_BREAK_ADDR 0x8021820
#define NIOS2_CPU_FREQ 50000000u
#define NIOS2_CPU_ID_SIZE 1
#define NIOS2_CPU_ID_VALUE 0x00000000
#define NIOS2_CPU_IMPLEMENTATION "fast"
#define NIOS2_DATA_ADDR_WIDTH 0x1c
#define NIOS2_DCACHE_LINE_SIZE 0
#define NIOS2_DCACHE_LINE_SIZE_LOG2 0
#define NIOS2_DCACHE_SIZE 0
#define NIOS2_EXCEPTION_ADDR 0x8010020
#define NIOS2_FLUSHDA_SUPPORTED
#define NIOS2_HARDWARE_DIVIDE_PRESENT 0
#define NIOS2_HARDWARE_MULTIPLY_PRESENT 1
#define NIOS2_HARDWARE_MULX_PRESENT 0
#define NIOS2_HAS_DEBUG_CORE 1
#define NIOS2_HAS_DEBUG_STUB
#define NIOS2_HAS_JMPI_INSTRUCTION
#define NIOS2_ICACHE_LINE_SIZE 32
#define NIOS2_ICACHE_LINE_SIZE_LOG2 5
#define NIOS2_ICACHE_SIZE 4096
#define NIOS2_INST_ADDR_WIDTH 0x1c
#define NIOS2_NUM_OF_SHADOW_REG_SETS 0
#define NIOS2_RESET_ADDR 0x8010000


/*
 * Define for each module class mastered by the CPU
 *
 */

#define __ALTERA_AVALON_NEW_SDRAM_CONTROLLER
#define __ALTERA_AVALON_ONCHIP_MEMORY2
#define __ALTERA_AVALON_PIO
#define __ALTERA_NIOS2_QSYS
#define __ETH_RX
#define __ETH_TX
#define __FIFO_TO_AMM


/*
 * System configuration
 *
 */

#define ALT_DEVICE_FAMILY "Cyclone IV E"
#define ALT_IRQ_BASE NULL
#define ALT_LOG_PORT "/dev/null"
#define ALT_LOG_PORT_BASE 0x0
#define ALT_LOG_PORT_DEV null
#define ALT_LOG_PORT_TYPE ""
#define ALT_NUM_EXTERNAL_INTERRUPT_CONTROLLERS 0
#define ALT_NUM_INTERNAL_INTERRUPT_CONTROLLERS 1
#define ALT_NUM_INTERRUPT_CONTROLLERS 1
#define ALT_STDERR "/dev/null"
#define ALT_STDERR_BASE 0x0
#define ALT_STDERR_DEV null
#define ALT_STDERR_TYPE ""
#define ALT_STDIN "/dev/null"
#define ALT_STDIN_BASE 0x0
#define ALT_STDIN_DEV null
#define ALT_STDIN_TYPE ""
#define ALT_STDOUT "/dev/null"
#define ALT_STDOUT_BASE 0x0
#define ALT_STDOUT_DEV null
#define ALT_STDOUT_TYPE ""
#define ALT_SYSTEM_NAME "qsys_eth"


/*
 * eth_rx_0 configuration
 *
 */

#define ALT_MODULE_CLASS_eth_rx_0 eth_rx
#define ETH_RX_0_BASE 0x8022200
#define ETH_RX_0_IRQ -1
#define ETH_RX_0_IRQ_INTERRUPT_CONTROLLER_ID -1
#define ETH_RX_0_NAME "/dev/eth_rx_0"
#define ETH_RX_0_SPAN 256
#define ETH_RX_0_TYPE "eth_rx"


/*
 * eth_tx_0 configuration
 *
 */

#define ALT_MODULE_CLASS_eth_tx_0 eth_tx
#define ETH_TX_0_BASE 0x8022100
#define ETH_TX_0_IRQ -1
#define ETH_TX_0_IRQ_INTERRUPT_CONTROLLER_ID -1
#define ETH_TX_0_NAME "/dev/eth_tx_0"
#define ETH_TX_0_SPAN 256
#define ETH_TX_0_TYPE "eth_tx"


/*
 * fifo_to_amm_0 configuration
 *
 */

#define ALT_MODULE_CLASS_fifo_to_amm_0 fifo_to_amm
#define FIFO_TO_AMM_0_BASE 0x8022000
#define FIFO_TO_AMM_0_IRQ -1
#define FIFO_TO_AMM_0_IRQ_INTERRUPT_CONTROLLER_ID -1
#define FIFO_TO_AMM_0_NAME "/dev/fifo_to_amm_0"
#define FIFO_TO_AMM_0_SPAN 256
#define FIFO_TO_AMM_0_TYPE "fifo_to_amm"


/*
 * hal configuration
 *
 */

#define ALT_MAX_FD 32
#define ALT_SYS_CLK none
#define ALT_TIMESTAMP_CLK none


/*
 * mem_prog configuration
 *
 */

#define ALT_MODULE_CLASS_mem_prog altera_avalon_onchip_memory2
#define MEM_PROG_ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0
#define MEM_PROG_ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0
#define MEM_PROG_BASE 0x8010000
#define MEM_PROG_CONTENTS_INFO ""
#define MEM_PROG_DUAL_PORT 0
#define MEM_PROG_GUI_RAM_BLOCK_TYPE "AUTO"
#define MEM_PROG_INIT_CONTENTS_FILE "qsys_eth_mem_prog"
#define MEM_PROG_INIT_MEM_CONTENT 1
#define MEM_PROG_INSTANCE_ID "NONE"
#define MEM_PROG_IRQ -1
#define MEM_PROG_IRQ_INTERRUPT_CONTROLLER_ID -1
#define MEM_PROG_NAME "/dev/mem_prog"
#define MEM_PROG_NON_DEFAULT_INIT_FILE_ENABLED 0
#define MEM_PROG_RAM_BLOCK_TYPE "AUTO"
#define MEM_PROG_READ_DURING_WRITE_MODE "DONT_CARE"
#define MEM_PROG_SINGLE_CLOCK_OP 0
#define MEM_PROG_SIZE_MULTIPLE 1
#define MEM_PROG_SIZE_VALUE 65536
#define MEM_PROG_SPAN 65536
#define MEM_PROG_TYPE "altera_avalon_onchip_memory2"
#define MEM_PROG_WRITABLE 1


/*
 * mem_tst configuration
 *
 */

#define ALT_MODULE_CLASS_mem_tst altera_avalon_onchip_memory2
#define MEM_TST_ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0
#define MEM_TST_ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0
#define MEM_TST_BASE 0x8020000
#define MEM_TST_CONTENTS_INFO ""
#define MEM_TST_DUAL_PORT 0
#define MEM_TST_GUI_RAM_BLOCK_TYPE "AUTO"
#define MEM_TST_INIT_CONTENTS_FILE "qsys_eth_mem_tst"
#define MEM_TST_INIT_MEM_CONTENT 1
#define MEM_TST_INSTANCE_ID "NONE"
#define MEM_TST_IRQ -1
#define MEM_TST_IRQ_INTERRUPT_CONTROLLER_ID -1
#define MEM_TST_NAME "/dev/mem_tst"
#define MEM_TST_NON_DEFAULT_INIT_FILE_ENABLED 0
#define MEM_TST_RAM_BLOCK_TYPE "AUTO"
#define MEM_TST_READ_DURING_WRITE_MODE "DONT_CARE"
#define MEM_TST_SINGLE_CLOCK_OP 0
#define MEM_TST_SIZE_MULTIPLE 1
#define MEM_TST_SIZE_VALUE 4096
#define MEM_TST_SPAN 4096
#define MEM_TST_TYPE "altera_avalon_onchip_memory2"
#define MEM_TST_WRITABLE 1


/*
 * pio_0 configuration
 *
 */

#define ALT_MODULE_CLASS_pio_0 altera_avalon_pio
#define PIO_0_BASE 0x8022300
#define PIO_0_BIT_CLEARING_EDGE_REGISTER 0
#define PIO_0_BIT_MODIFYING_OUTPUT_REGISTER 1
#define PIO_0_CAPTURE 0
#define PIO_0_DATA_WIDTH 16
#define PIO_0_DO_TEST_BENCH_WIRING 0
#define PIO_0_DRIVEN_SIM_VALUE 0
#define PIO_0_EDGE_TYPE "NONE"
#define PIO_0_FREQ 50000000
#define PIO_0_HAS_IN 0
#define PIO_0_HAS_OUT 1
#define PIO_0_HAS_TRI 0
#define PIO_0_IRQ -1
#define PIO_0_IRQ_INTERRUPT_CONTROLLER_ID -1
#define PIO_0_IRQ_TYPE "NONE"
#define PIO_0_NAME "/dev/pio_0"
#define PIO_0_RESET_VALUE 0
#define PIO_0_SPAN 32
#define PIO_0_TYPE "altera_avalon_pio"


/*
 * pio_in configuration
 *
 */

#define ALT_MODULE_CLASS_pio_in altera_avalon_pio
#define PIO_IN_BASE 0x8022320
#define PIO_IN_BIT_CLEARING_EDGE_REGISTER 0
#define PIO_IN_BIT_MODIFYING_OUTPUT_REGISTER 0
#define PIO_IN_CAPTURE 0
#define PIO_IN_DATA_WIDTH 32
#define PIO_IN_DO_TEST_BENCH_WIRING 0
#define PIO_IN_DRIVEN_SIM_VALUE 0
#define PIO_IN_EDGE_TYPE "NONE"
#define PIO_IN_FREQ 50000000
#define PIO_IN_HAS_IN 1
#define PIO_IN_HAS_OUT 0
#define PIO_IN_HAS_TRI 0
#define PIO_IN_IRQ -1
#define PIO_IN_IRQ_INTERRUPT_CONTROLLER_ID -1
#define PIO_IN_IRQ_TYPE "NONE"
#define PIO_IN_NAME "/dev/pio_in"
#define PIO_IN_RESET_VALUE 0
#define PIO_IN_SPAN 16
#define PIO_IN_TYPE "altera_avalon_pio"


/*
 * sdram configuration
 *
 */

#define ALT_MODULE_CLASS_sdram altera_avalon_new_sdram_controller
#define SDRAM_BASE 0x0
#define SDRAM_CAS_LATENCY 3
#define SDRAM_CONTENTS_INFO
#define SDRAM_INIT_NOP_DELAY 0.0
#define SDRAM_INIT_REFRESH_COMMANDS 2
#define SDRAM_IRQ -1
#define SDRAM_IRQ_INTERRUPT_CONTROLLER_ID -1
#define SDRAM_IS_INITIALIZED 1
#define SDRAM_NAME "/dev/sdram"
#define SDRAM_POWERUP_DELAY 100.0
#define SDRAM_REFRESH_PERIOD 15.625
#define SDRAM_REGISTER_DATA_IN 1
#define SDRAM_SDRAM_ADDR_WIDTH 0x19
#define SDRAM_SDRAM_BANK_WIDTH 2
#define SDRAM_SDRAM_COL_WIDTH 10
#define SDRAM_SDRAM_DATA_WIDTH 32
#define SDRAM_SDRAM_NUM_BANKS 4
#define SDRAM_SDRAM_NUM_CHIPSELECTS 1
#define SDRAM_SDRAM_ROW_WIDTH 13
#define SDRAM_SHARED_DATA 0
#define SDRAM_SIM_MODEL_BASE 0
#define SDRAM_SPAN 134217728
#define SDRAM_STARVATION_INDICATOR 0
#define SDRAM_TRISTATE_BRIDGE_SLAVE ""
#define SDRAM_TYPE "altera_avalon_new_sdram_controller"
#define SDRAM_T_AC 5.5
#define SDRAM_T_MRD 3
#define SDRAM_T_RCD 20.0
#define SDRAM_T_RFC 70.0
#define SDRAM_T_RP 20.0
#define SDRAM_T_WR 14.0

#endif /* __SYSTEM_H_ */
